1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an SRAM (static random access memory) and an on-chip memory which is mounted on a system LSI.
2. Description of the Background
With the recent trend toward a decrease in the voltage applied to memory cells and a reduction in cell size, the problem of deterioration in soft error immunity has emerged. It is known that there are semiconductor integrated circuits which use an ECC (Error Correction Code) circuit to correct such data errors, as illustrated by JP-A-50295/1986 and JP-A-45096/1995. JPA-45096/1995 discloses a circuit technology which corrects a fail bit by adding a parity bit to normal data. JP-A-212877/1999 discloses a circuit technology which rewrites part of data which has the same parity bit.
However, in the method given by JP-A-45096/1995, all data in an array must be read in sequential order to correct an error at the time of reading and it is impossible to read, correct, and output data in a single cycle.
Also, in the method given by JP-A-212877/1999, data and a parity bit are read, part of the corrected data is replaced with written data, and a parity bit is regenerated. Only the regenerated parity bit and written data are rewritten, but the corrected bits cannot be rewritten.